| Filename | Quartus II 11.1 SP1 Build 216 Altera Complete Design Suite |
| Permission | rw-r--r-- |
| Author | AuLia Al Fajr |
| Date and Time | 19.55 |
| Label | Programing |
| Action |
Quartus II 11.1 SP1 Build 216 Altera Complete Design Suite� (Linux) | 3.71 GB
Enhanced suppt f Stratix V FPGA, namely: Suppts GigE and SDI embedded transceivers; now suppt setting additional transceivers. parameters (receiver offset calibration, linear equalizer, and dynamic reconfiguration of PMA analog settings). Added debugging interface to external memy chips (Memy Interface Toolkit). The new facility allegedly allows realtime track the perfmance of the memy subsystem.
You can choose the most efficient mode of operation of the memy controller, changing its settings. Added a debugging tool f the transceiver (Transceiver Toolkit). Improved user interface manager channels enables realtime monit link status of receivers and transmitters. Enhanced control panel lets the channels on the fly to change the parameters of transceivers and see how it affects the system.
All this allows developers to rapidly build and debug the board. There was a better means of rapid establishment of the project instead of QSys SOPS Builder. Allows you to quickly connect QSyscompatible IPCes blocks into a single system.
Additional improvements:
Improved Chip Planner (As f the settings of transceivers Stratix FPGA V);
adds suppt f 64bit Windows and Linux f the DSP Builder
added another IP Ce Deinterlacer II IP ce
improved suppt f Cyclone IV GX FPGAs and MAX V CPLDs (see final timing model can be generated and POF).
Finally Improved the problem with the Cyrillic alphabet in a text edit!))
SOURCE LINK : http://just4freeplanet.com
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